1. Field of the Invention
The present invention relates to a jitter suppression circuit, and in particular to a jitter suppression circuit for suppressing jitter components which occur when an optical output signal is provided from an electric input data signal in an optical transmission circuit.
2. Description of the Related Art
An optical transmission circuit, in which it is required to provide a high-quality and stable optical signal independently of a waveform or the like of an electric input data signal, encounters a problem of jitter components (hereinafter, occasionally referred to as phase deviations) in the electric input data signal. The jitter components will now be briefly described.
FIG. 5A shows a format used for a SONET (Synchronous Optical NETwork) or an SDH (Synchronous Digital Hierarchy). In the case of the SONET, a single STS-N frame is composed of N×90 columns×9 rows, as shown in FIG. 5A, having a transport overhead composed of N×3 columns×9 rows on the left side and a payload of the STS-N frame occupying the other parts.
FIG. 5B shows an enlarged view of the transport overhead when N in FIG. 5A is supposed to be 3 (N=3), where a frame synchronous pattern is formed of A1 bytes and A2 bytes in a section overhead (SOH).
In the case of the SONET signal (or SDH signal) of 10 Gbps which is getting prevalent, N is 192. Accordingly, when the repetition of the fixed synchronous pattern continues for a long time (about 300 ns in total of both A1 bytes and A2 bytes), phase deviations which have occurred in the A1 bytes and the A2 bytes have a frequency component of about 3 MHz. Furthermore, the fixed pattern is repeated similarly for the Z0 bytes, so that the fixed pattern continues for about 460 ns in total.
FIGS. 6A and 6B show effects of such a fixed pattern which continues for a long time.
Namely, upon normal time shown in FIG. 6A, an electric input data signal waveform shown in FIG. 6A(a) shows a state where phase deviations (jitter components) of a header portion (a header portion of the SONET signal (OC-192) in this case) due to the fixed pattern become large like an optical output signal as shown in FIG. 6A(b). Also, when the input waveform deteriorates as shown in FIG. 6B, the electric input data signal waveform shown in FIG. 6B(a) has phase deviations of the header portion further increasing as shown in FIG. 6B(b).
For such phase deviations, SONET prescribes values equal to or less than 0.1 UIpp for the jitter standard. Accordingly, a case where the phase deviations exceed 0.1 UIpp raises a problem.
On the other hand, when the optical signal is outputted based on the input data signal including the jitter components based on such a fixed pattern, an arrangement as shown in FIG. 7A has been hitherto known where a high-quality synchronizing clock signal CLKs synchronized with the input data signal is transferred by a D-FF (Flip Flop) 7 and the data signal regenerated by the D-FF 7 is passed through a driving circuit 5 and an optical modulator 6 to generate an output optical signal Os. Thus, it is possible to generate the output optical signal Os from an input data signal Es without being affected by the jitter components.
However, in a recent optical communication module, transferring the synchronizing clock signal CLKs as shown in FIG. 6A tends to be omitted because of thorough downsizing, simplification of an interface, and the like. Accordingly, in the absence of such a synchronizing clock, jitter components of the input data signal are not suppressed and so transferred to the optical signal, so that the jitter components of the output optical signal increase as shown in FIG. 6B.
As an example not using such a synchronizing clock signal, another prior art shown in FIG. 7B has been known. In this prior art, firstly in order to remove the jitter components included in the input data signal Es to some extent, the input data signal Es is passed through a broadband CDR (Clock & Data Recovery) circuit 1, and a clock CLK of a bit rate of the input data signal is extracted in an installed PLL circuit (not shown). Also, the jitter components are filtered by a broadband lowpass filter of about 8 MHz within the PLL circuit, so that data DATA is regenerated. It is to be noted that setting to a narrow band can not be achieved in this case because the regenerated data may have an error due to a clock extracted by a narrowband PLL circuit when the input data signal Es with the jitter components is tapped or sampled.
Namely, in order to avoid a code error occurrence, there is a limit of the suppression of the jitter components included in the input signal. In the SONET standard, even if a signal with 1.5 UIpp jitters is inputted e.g. at a frequency of 400 kHz, code errors must not be generated. If jitter components of 400 kHz are completely suppressed, the code errors occur as for the signal with the jitter components exceeding 1 UI without fail. Accordingly, it is required to transmit jitters to some extent without suppression, so that the CDR circuit 1 normally has a broadband of about 8 MHz.
On the other hand, if a transparent bandwidth of jitters is about 8 MHz, jitter components of about 3 MHz which occur at A1 and A2 bytes can not be suppressed, so that the output signal is to hold the jitter components.
Therefore, the data DATA and the clock CLK thus outputted from the broadband CDR circuit 1 are transmitted to an FIFO 8 composed of plural stages of shift registers, and the clock CLK is also transmitted to a narrowband PLL circuit 9.
The narrowband PLL circuit 9, in response to the clock CLK, passes the jitter components through a lowpass filter (not shown) of e.g. 100 KHz to generate a read clock of the above-mentioned bit rate, by which the data DATA stored in the FIFO 8 is re-tapped, whereby the output optical signal Os with few jitter components is generated through the driving circuit 5 and the optical modulator 6.
On the other hand, there is a data transmission rate determining device which synchronizes a reception timing of data transmitted from other data transmitters/receivers at a synchronous circuit based on a transmission rate of data determined by a determining portion, and which processes the data received by using the synchronous circuit at a processing circuit (see e.g. patent document 1).
Also, there is a transmission rate detection circuit detecting each transmission rate of a synchronous transfer mode (STM-M) corresponding to the SDH (see e.g. patent document 2).
Furthermore, there is a circuit which detects normalized phase jitters, predicts subsequent phase jitters from the detected phase jitters, and predicts subsequent phase jitters by averaging to the detected phase jitters (see e.g. patent document 3).    [Patent Document 1] Japanese Patent Application Laid-open No. 2003-60732    [Patent Document 2] Japanese Patent Application Laid-open No. 2000-286922    [Patent Document 3] Japanese Patent Application Laid-open No. 2003-134178
While the prior art shown in FIG. 7A requires the synchronizing clock signal, the prior art shown in FIG. 7B, which suppresses the jitter components without the synchronizing clock signal, has to use the narrowband PLL circuit and the FIFO.
Namely, in the latter case, a VCO (voltage controlled oscillator) used for the narrowband PLL circuit 9 is inevitably attached as an external part, resulting in a problem that a circuit scale grows.